1326AB-B720E-21-K7
1326AB-B720E-21-K7
1326AB-B720E-21-K7
系统采用模块化的设计方法，将整个系统划分为三部分：视频采集单元、视频处理单元和视频传输单元。
整个系统以FPGA作为核心控制单元并完成视频信号的中值滤波工作;以DSP作为整个系统的核心处理单元对采集的视频图像信息进行JPEG压缩;在视频传输单元设计了以PDIUSBD12芯片为基础的USB总线，负责视频信号的传输。
1 系统硬件体架构
一个完整的视频处理系统，主要由视频采集单元、视频处理单元及视频传输单元三部分组成。在进行系统设计时须确保各部分的无缝衔接。
图像采集单元由FPGA和MB86S02视频采集芯片组成，包括视频信号的采集和预处理，把输入的视频信号转换成系统能够处理的数字图像数据，并按照一定的格式存储在确定的存储区域。
图像处理单元是本系统的核心，对图像数据进行压缩处理，实现系统要达到的功能。
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